Volatco - Powerful Multicompute

The most powerful environmentally-friendly computing hardware that can run independently of grid power and data. An advanced polyForth development board where programming machine intelligence and other autonomous applications leverages the extreme low-power (1.8 VDC) compute of 16MB (1-bit precision) SPI and 128MB SRAM with 144-asynchronous nodes configured in HOST and TARGET chips where much of their I/O are connected as header-pins.

Introducing Volatco

The first widely-available multicomputer and multiprogrammer for machine-intelligent ideal applications in a compact 6 cm x 4 cm x 1.5 cm form-factor.

What is a Volatco?

A machine-intelligent capable off-power board that provides compute to explore embodied AI, neuromorphic experimentation, and ultra‑low‑energy inference, with robust hardware that is massively parallel, energy‑frugal, and easily extensible with certified plug-ins.

The Volatco multicomputer packs two GA144A12 mesh‑processor chips, 16 MB of SRAM, 16 MB of SPI flash, and a flexible off‑board I/O architecture into a board smaller than a credit card that draws only milliwatts of power when idle.

Plug-ins: Dedicated power, Ethernet, and Bluetooth.

polyForth: On-board operating system that is lightweight, dual-stack operating system and programming environment.

Key Features

The information below pertains to the technical details of a Volatco.

The Volatco pin-set

All connections are made on the top of the PCB. The model ‘c’ dialect has pins out both the top and bottom of the board.

Option Jumpers

• J6 is “No boot”. Insert to prevent chip 0 from booting SPI flash on reset.
• J5 selects development mode (pins 1 and 2 jumpered) or production (pins 2 and 3). In the latter case the watchdog/reset circuit is enabled. Development mode is required whenever “No boot” is installed.
• J4 is shorted to produce a manual reset. This may also be done by the system providing IDE service through J8. Either of these reset methods works in either development or production mode.

Connection Headers

• J1 is external power and ground input.
• J8 is for serial IDE input (including reset).
• J7 is for polyFORTH terminal input - including watchdog signal, normally supplied from on the board. Both J7 and J8 carry both ground and V1P8 for devices such as FTDI chips that can accept our supply to power their I/O pins.
• J9 and J10 are signals from chip 0 plus two pins from chip 1. J11, J12, and J13 all carry signals from chip 1. Each of these 12-pin headers carries 9 signals and 3 grounds, for a total of 45 signals. See following table for the pinout description.

Power control

Note that the ground pins are those nearest the PCB edge.

Jumpers are shown for normal operation. Substitute a shunt resistor to measure voltage drop across the resistor and calculate current. Be sure to use a small enough value that the expected current will not cause a voltage drop setting the supply below specs for the chip (typically 1.62V).

Note that unlike J2 the incoming supply is on the right side of this jumper block. The polarity of the drop will be reversed accordingly.

Manual reset

Short these pins together to assert reset on chip 0. Works in whether or not watchdog is enabled.

Operating modes

The manual/external reset always goes to the reset input of the watchdog chip. This jumper selects which signal goes to chip 0: The manual/external reset signal, or the output of the watchdog. Normal field production mode, enabling watchdog, is shown as the default. The watchdog should be disabled by moving the jumper to pins 1 and 2, when not running the production code on the chips.

No boot

Install this jumper to prevent program booting from the SPI flash. When this is installed, the watchdog must be disabled by connecting pins 1 and 2 of J5.

Programmer access

This serial port supports an asynchronous serial terminal for polyFORTH running on chip 0. Pin 6 must be jumpered or wire wrapped to a pin generating watchdog pulses before the watchdog may be enabled.

This serial port is used to talk to nodes on one or both chips directly using the Interactive Development Environment via node 708 of chip 0. Its reset pin is effective in both operating modes. Once the SPI flash has been initialized with boot code, this port is not necessary to run polyFORTH.

Signal access

Be aware that pin 9 10708.17 is input to a boot node. If pin is being driven high by another device when chip 1 is reset, node 10708 will delay for a long time during boot which may cause problems with watchdog. If being used as an output and driven high on reset, the RC time constant of load capacitance and weak pull down resistance may be long enough to delay booting. The same is true of 10705.17 if being used as an input and driven low by another device during reset.